Modern electronics such as high-performance microprocessor and digital signal processor systems increasingly require a plurality of voltage levels. Care must be taken to power up and down the corresponding voltage rails. Internal circuits suffer stress if certain power rails are active while others are inactive. In addition, microprocessors may suffer latch-up, which damages or destroys affected transistors. As a result, power up and power down sequencing must be practiced to prevent these problems.
Power supply sequence controllers enable circuit designers to meet the need for power sequencing in their designs. A programmable sequence controller comprises a programmable logic device (PLD) that a user programs according to the particular power sequence control desired. An example programmable sequence controller is disclosed in U.S. patent application Ser. No. 09/732,216 entitled “Programmable Power Management System and Method,” filed Dec. 6, 2000, which is hereby incorporated by reference in its entirety. Generally, programming a PLD involves writing a hardware-description-language-(HDL)-based source code. Although the use of HDL is widespread, writing HDL code is complicated and involves a substantial amount of overhead, even for the relatively simple designs involved in power sequence control. In addition, the configurability of the programmable logic in power sequence controllers substantially adds to the burden of writing the necessary HDL source code.
Accordingly, there is a need in the art for improved techniques to program power sequence controllers.